Power management chip design engineer

Job description

Development of highly integrated power management chips
Job requirements
1. Bachelor degree or above in chip design/microelectronics/electronic engineering or related major
2. More than 2 years analog circuit design experience, experience in power management chip design is preferred
3. Master the basic principles and theoretical knowledge of power management technology, including lithium battery charging IC, lithium battery protection IC, DC-DC boost IC, DC-DC step-down IC, LED Driver, Charge Pump, LDO IC, battery charging management, etc
4. Familiar with CMOS process, understanding of high pressure process and BCD process is preferred
5. Familiar with transistor level analog integrated circuit design and verification methods
6. Familiar with analog circuit design EDA tools
7. Other high precision, low power analog IC design experience is preferred
8. Complete Layout layout, layout optimization and post-copy verification with layout
9. Develop a test plan
10. Assist FAE to solve problems encountered by the client
11. Work hard, patient, proactive, have certain ability to work under pressure, and have good communication and teamwork skills

Power management chip layout design engineer

Job description

1.according to the line to do forward analog layout design
2. Complete DRC, LVS, ERC verification
Job Requirements:
1. Bachelor degree or above in chip design/microelectronics/electronic engineering or related major
2. Familiar with integrated circuit process and basic knowledge of circuits
3. Understand the knowledge of forward analog layout, such as matching, noise, parasitism, etc
4. Understand antenna effects, Latch_up and ESD circuits
5. Proficient in Virtuoso, Calibre and other EDA software
6. Work hard, patient, proactive, have certain ability to work under pressure, and have good communication and teamwork skills